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system - management ic with programmable quad voltage monitoring and supervisory functions preliminary technical data ad5100 rev. prj information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features ? two device-enabling outputs with six programmable monitoring inputs (table 1) o two 30v monitoring inputs with shutdown control of external devices: ? programmable over-voltage, under-voltage, turn-on, turn-off thresholds, and shutdown timings ? shutdown warning with fault detection o t wo 5v monitoring inputs with reset control of external devices: ? programmable reset thresholds and hold time o two supervisory functions: ? watchdog reset controller with programmable timeout and selectable floating input ? manual reset control for external devices ? digital interface and programmability: o i 2 c ? compatible interface o otp 1 for permanent threshold and timing settings o otp overwritten capable for dynamic adjustments o power up by edge triggered signal o power down by i 2 c software ? operating range: o supply voltage 6.0v to 30v o temp range -40 o c to +125 o c o low shutdown current: 10a ? high-voltage-input anti-migration shielding pinouts applications ? automotive systems ? network equipment ? computers, controllers, and embedded systems general description the ad5100 is a programmable system-management ic that combines 4-channel of voltage monitoring and a watchdog supervision that can be used to shutdown external supplies, reset processors, or disable any other system electronics when the systems malfunction. the ad5100 can also be used to protect system under faulty condition of improper devices power up sequencing. the ad5100 can monitor two 30v inputs with shutdown and reset controls, one 2.5v-5.0v and one 0.9v- 3.3v monitoring inputs with reset control, a robust watchdog reset controller. most monitoring input thresholds and timing settings can be programmed on the fly or permanently set in the factory with the otp feature. the ad5100 is versatile for system-monitoring applications where critical p, dsp, and embedded systems operate under harsh conditions such as automotive, industrial, or communications network environments. the ad5100 is available in compact qsop-16 and can operate in an extended automotive temperature range from -40 o c to +125 o c. 1 .one time programmable eprom C unlimited adjustment before otp execution. 2 with programmable threshold and programmable delay. table 1. ad5100 general inputs and output information input monitoring range 2 shutdown control reset cont rol fault dete ctio n v 1mon 6 C 30 v v 2mon 3 C 30 v v 3mon 2.5 C 5.0 v v 4mon 0.9 C 3.3 v wdi 0 C 5 v mr 0 C 5 v
ad5100 preliminary technical data rev. prj | page 2 of 32 functional block diagram figure 1. functional block diagram
preliminary technical data ad5100 rev. prj | page 3 of 32 electrical characteristics 6v v 1mon 30v and 3v v 2mon 30v, -40c t a +125c, unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit high-voltage monitoring inputs v 1mon , v 2mon and shdn , shdnwarn output input resistance r in_v1mon, r in_v2mon 60 k v 1mon ov, uv threshold tolerance ov, uv t a = 25 o c -1.5 +1.5 % (figure 5 and table 5a) t a = -40 o c to 85 o c -2 +2 % t a = -40 o c to 125 o c -3 +3 % hysteresis 1.5 % programmable shutdown hold time tolerance (figure 5 and table 6a) t 1sd_hold does not apply to code 0x7 -10 +10 % programmable shutdown delay tolerance (figure 4 and table 6a) t 1sd_delay does not apply to code 0x7 -10 +10 % fault detection delay t fd_delay 70 s glitch-immune time t glitch 50 s v 2mon on, off threshold tolerance 2 on, off t a = 25 o c -1.5 +1.5 % (figure 5 and table 5a) t a = -40 o c to 85 o c -2 +2 % t a = -40 o c to 125 o c -3 +3 % hysteresis 1.5 % turn-on programmable shdn hold time tolerance (figure 5 and table 6a) t 2sd_hold does not apply to code 0x7 -10 +10 % turn-off programmable shdn delay time tolerance (figure 5 and table 6a) t 2sd_delay does not apply to code 0x7 -10 +10 % fault detection delay t fd_delay v 2mon_off only 70 s glitch immune time t glitch 50 s shdn shdn output high v oh v rail =v reg , i source =40ua 2.4 v shdn output high v oh v rail =v 1mon , i source =600ua v 1mon -0.5 v shdn output low v ol i sink =1.6ma 0.4 v shdn output low v ol v 1mon =12v, i sink =40ma 1.7 3 v shdn sink current i sink v 1mon =12v, shdn forced to 12v 10 15 ma shdnwarn (open drain output) shdnwarn inactive leakage current i oh_shdnwarn 1 a shdnwarn active v ol_shdnwarn isink = 3ma 0.4 v low-voltage monitoring inputs v 3mon , v 4mon and reset output voltage range v 3mon , v 4mon -0.3 5.5 v input resistance r in_v1mon, r in_v2mon 50 k v 3mon, v 4mon v 3mon threshold tolerance v 3mon t a = 25 o c -1.5 +1.5 % (figure 6 and table 5a) t a = -40 o c to 85 o c -2 +2.7 % t a = -40 o c to 125 o c -3 +3.5 % v 3mon hysteresis v 3_hysteresis 1.5 %
ad5100 preliminary technical data rev. prj | page 4 of 32 parameter symbol conditions min typ 1 max unit v 4mon threshold tolerance v 4mon t a = 25 o c -2.5 +2.5 % (figure 7 and table 5a) t a = -40 o c to 85 o c -3 +3 % t a = -40 o c to 125 o c -3.5 +3.5 % v 4mon hysteresis v 4_hysteresis 6 % reset hold time tolerance (figures 6, 7, and table 6a) t rs_hold does not apply to codes 0x6 and 0x7 -10 +10 % v 3,4mon Cto-reset delay t rs_delay 70 s reset output voltage v oh v 3mon 4.38v, i source = 120ua v 3mon -1.5 v 2.7v < v 3mon 4.38v, i source = 30ua 0.8xv 3mon v 2.3v < v 3mon 2.7v, i source = 20ua 0.8xv 3mon v 1.8v v 3mon 2.3v, i source = 8ua 0.8xv 3mon v v ol v 3mon > 4.38v, i sink = 3.2ma 0.4 v v 3mon < 4.38v, i sink = 1.2ma 0.3 v reset output short-circuit current 3 i source reset = 0, v 3mon = 5.5v 800 a reset = 0, v 3mon = 3.6v 400 a glitch immune time t glitch 50 s v 4out maximum output v 4out_max open drain 5.5 v v 4out propagation delay t v4out_delay 70 s v 4out maximum frequency f v4out apply to reset disabled only 10 khz wdi (watchdog input) wdi programmable-timeout tolerance (figure 8 and table 6a) t wd -10 +10 % wdi pulse width t wdi 50 ns watchdog-initiated reset pulse width t wdr when no wdi t wd /50 ms watchdog-initiated shdn t wd_shdn when no wdi activity > 4 t wd 1 s wdi input voltage v il_wd 0.3xv 3mon v v ih_wd 0.7xv 3mon v wdi input current wdi = v 3mon , time average 160 a wdi = 0, time average -20 a mr ( manual reset) input mr input voltage v il_mr 0.3*v 3mon v v ih_mr 0.7*v 3mon v mr pulse width t mr 1 s mr deglitching t mr_glitch 100 ns mr -to-reset delay t mr_delay 1 s mr pullup resistance (internal to v3mon) 50 k reset hold-time tolerance (figure 9 and table 6a) t rs_hold do not apply to codes 0x6 and 0x7 -10 +10 % serial interfaces input logic high (scl, sda) 4 v ih external rpull-up = 2.2k 2.0 5.5 v input logic low (scl, sda) v il external rpull-up = 2.2k 0 0.8 v output logic high (sda) v oh v rail = 3.3v, external rpull-up = 2.2k 3.0 3.3 v output logic low (sda) v ol v rail = 3.3v, external rpull-up = 2.2k 0 0.4 v input capacitance c i 5 pf power supply supply voltage range v 1mon 6.0 30 v
preliminary technical data ad5100 rev. prj | page 5 of 32 parameter symbol conditions min typ 1 max unit sleep mode supply current i sleep_v1mon v 2mon = 0 v 10 a active mode supply current i power_v1mon v 2mon = 12 v 3 ma v 2mon edge triggered mode selected 3 ma device power on threshold v2mon,ih 2.2 v v2mon,il 0.4 v device power up v2mon minimum pulse width (figure 14) t v2mon_pw 4 ms device power down delay v2mon < 0.4v (normal mode) 2 s i2c initiated power down 10 s otp supply voltage 6 v otp for otp only 6 6.5 v otp supply current i votp for otp only 200 ma otp settling time 7 t s_otp 12 ms timing characteristics 8 parameter adjustment time t s1 1 s i2c interface timing characteristics scl clock frequency f scl 400 khz t buf bus free time between start and stop t 1 1.3 s t hd;sta hold time after (repeated) start condition. after this period, the first clock is generated t 2 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 50 s t su;sta setup time for start condition t 5 0.6 s t hd;dat data hold time t 6 0.9 s t su;dat data setup time t 7 0.1 s t f fall time of both sda and scl signals t 8 0.3 s t r rise time of both sda and scl signals t 9 0.3 s t su;sto setup time for stop condition t 10 0.6 s notes: 1. represent typical values at 25c, v 1mon = 12 v, and v 2mon = 12 v. 2. does not apply if v 2mon is a digital signal. 3. the reset short-circuit current is the maximum pullup current when reset is driven low by a p bidirectional reset pin. 4. it is typical for the scl and sda have resistors to be pulled up to v 3mon . however, care must be taken to ensure that the minimum v ih is met when the scl and sda are driven directly from a low voltage logic controller without pull-up resistors. 5. initial v 2mon on minimum remains as 2.2v but the -0.3v to 30v specifications apply afterwards. 6. v otp can be furnished by factory 6v power supply, rather than on-board power supply, when performing factory programming. a 10uf ta ntalum capacitor is required on v otp during operation regardless of whether the otp fuses are programmed. 7. the otp settling time occurs only once if otp function is used. 8. guaranteed by design and not subject to production test. 04104-0-044 t 1 t 2 t 3 t 8 t 8 t 9 t 9 t 6 t 4 t 7 t 5 t 2 t 10 ps s scl sda p figure 2. digital interface timing diagram
ad5100 preliminary technical data rev. prj | page 6 of 32 absolute maximum ratings table 3. parameter rating v 1mon to gnd ?0.3 v, +33 v v 2mon to gnd ?0.3 v, +33 v v 3mon to gnd ?0.3 v, +7 v v 4mon to gnd ?0.3 v, +7 v v otp to gnd ?0.3 v, +7 v digital input voltage to gnd (mr , wdi, scl, sda, ad0) 0 v, +7v digital output voltage to gnd (reset ,v 4out, shdnwarn ) 0 v, +7v digital output voltage to gnd (shdn ) 0 v, +33v operating temperature range ?40c to +125c hbm esd (all pins) 2kv maximum junction temperature (t j max) 140c storage temperature ?65c to +150c lead temperature (soldering, 10 s C 30 s) 245c thermal resistance junction-to- ambient 1 ja 105 o c/w thermal resistance junction-to-case jc 39 o c/w 1 package power dissipation = (t j max C t a ) / ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
preliminary technical data ad5100 rev. prj | page 7 of 32 pin configuration and fu nctional description figure 3a. ad5100 pin configuration gnd 1 2 3 4 16 14 13 5 6 7 8 12 11 10 9 15 ad5100 gnd 1 2 3 4 16 14 13 5 6 7 8 12 11 10 9 15 ad5100 figure 3b. recommended pcb layout for shielded high-voltage inputs table 4. ad5100 pin function descriptions pin no. mnemonic description 1 v 1mon high-voltage monitoring input. ad5100 internal supply is derived from v 1mon.. 2 gnd ground. 3 v otp one-time supply voltage for eprom. can be floati ng when it is not performing fuse programming 4 v 3mon low-voltage monitoring-input 5 mr manual-reset input. active-low. 6 wdi watch-dog input. 7 scl i2c serial-input register clock. if it is driven directly from a logic driver without the pull-up resistor, ensure that v ih min is 3.3v. 8 sda i2c serial data input/output. if it is driven direct from a logic driver without the pull-up resistor, ensure that v ih min is 3.3v. 9 reset reset , push-pull output with rail voltage of v 3mon 10 v 4out open-drain output. triggered by v 4mon 11 shdnwarn shutdown warning. active-low, open-drain output. 12 shdn shutdown output. push-pull output wi th selectable rail voltage of v 1mon or v reg . 30v maximum 13 ad0 i2c slave-address configuration. 14 v 4mon low-voltage monitoring input. 15 gnd/nc ground/no connect. can be grounded or left floating but do not connect to any other potentials. 16 v 2mon high-voltage monitoring input. it is also the internal-supply-voltage enabling input. v 1mon gnd v 3mon v otp scl sda wdi v 2mon v 4out ad0 1 6 1 5 1 4 1 3 1 2 11 10 9 1 2 3 4 5 6 7 8 ad5100 shdn gnd/nc reset v 4mon mr shdnwarn
ad5100 preliminary technical data rev. prj | page 8 of 32 table 5a. available programmable-threshold at t a = 25 o c (all values are typical ratings; see table 2 for tolerances) v 1mon ov threshold v 1mon uv threshold v 2mon on threshold v 2mon off threshold v 3mon threshold v 4mon threshold 7.92 6.00 3.00 3.00 2.32 disabled* 9.00 6.49 3.30 3.30 2.64 0.86 9.90 6.95 4.50 4.50 2.93 1.15 11.00 7.47 4.77 4.77 3.10 1.37 12.00 7.92 6.00 6.00 4.36* 1.43 13.20 8.43* 6.49 6.49 4.65 1.66 14.14 9.00 6.95 6.95* 4.75 2.30 15.23 9.43 7.47* 7.47 4.97 3.10 15.84 9.90 7.92 7.92 reserved reserved 17.22 10.42 8.43 8.43 reserved reserved 18.00* 11.00 9.00 9.00 reserved reserved 18.86 11.65 9.43 9.43 reserved reserved 19.80 12.00 9.90 9.90 reserved reserved 22.00 12.38 15.23 15.23 reserved reserved 24.75 13.20 19.80 19.80 reserved reserved 28.29 13.66 24.75 reserved reserved rising edge trigger/pseudo can wake up mode * default. v 1mon_ov must be > v 1mon_uv . v 2mon_off will be ignored if > v 2mon_on but v 2mon_off cannot be = v 2mon_on . table 5b. look up table of programming code versus typical thresholds shown in table 5a code v 1mon ov threshold v 1mon uv threshold v 2mon on threshold v 2mon off threshold v 3mon threshold v 4mon threshold 0000 18.00* 8.43* 7.47* 6.95* 4.36* disabled* 0001 18.86 7.92 6.95 7.47 4.65 0.86 0010 15.84 9.43 6.49 6.00 4.75 1.15 0011 17.22 9.00 6.00 6.49 4.97 1.37 0100 24.75 6.49 4.77 4.50 2.32 1.43 0101 28.29 6.00 4.50 4.77 2.64 1.66 0110 19.80 7.47 3.30 3.00 2.93 2.30 0111 22.00 6.95 3.00 3.30 3.10 3.10 1000 9.90 12.38 24.75 19.80 reserved reserved 1001 11.00 12.00 19.80 reserved reserved rising edge trigger/pseudo can wake up mode 1010 7.92 13.66 15.23 9.90 reserved reserved 1011 9.00 13.20 9.90 15.23 reserved reserved 1100 14.14 10.42 9.43 9.00 reserved reserved 1101 15.23 9.90 9.00 9.43 reserved reserved 1110 12.00 11.65 8.43 7.92 reserved reserved 1111 13.20 11.00 7.92 8.43 reserved reserved
preliminary technical data ad5100 rev. prj | page 9 of 32 table 6a. available programmable hold time and delay (all values are typical ratings; see table 2 for tolerances) t 1sd_hold (ms) t 1sd_delay (ms) t 2sd_hold (ms) t 2sd_delay (ms) t rs_hold (ms) t wd (ms) 0.07 0.07 0.07 0.07 0.1 100 20 50 10* 50 1 250 40 100 20 100* 15 500 60 200 30 200 30 750 80 400 40 400 50 1000 100 800 50 800 100 1250 150 1000 100 1000 150 1500* 200* 1200* 200 1200 200* 2000 * default table 6b. look up table of programming code versus typical timings shown in table 6a code t 1sd_hold (ms) t 1sd_delay (ms) t 2sd_hold (ms) t 2sd_delay (ms) t rs_hold (ms) t wd (ms) 000 200* 1200* 10* 100* 200* 1500* 001 150 1000 20 50 150 2000 010 100 800 30 200 100 1250 011 80 400 40 400 50 1000 100 60 200 50 800 30 750 101 40 100 100 1000 15 500 110 20 50 200 1200 1 250 111 0.07 0.07 0.07 0.07 0.1 100 * default
ad5100 preliminary technical data rev. prj | page 10 of 32 theory of operation the ad5100 is a programmable system management ic that has four channels of monitoring inputs. two inputs have high voltage (30v) capability. for example if the ad5100 is used in the automotive application, the v 1mon (monitoring input 1) should be the battery and the v 2mon should either be the ignition switch or the pseudo can bus wake up signal input. two other inputs, v 3mon and v 4mon , are low voltage for 0.9v, 1.8v, 2.5v, 3.3v, or 5v monitoring. the two high voltage inputs control the shutdown signal, shdn , while the two low voltage inputs control the reset signal, reset . the shdn and reset are both disabling functions for the external devices. the differences are output levels and driving capabilities that will be described later. in some cases the shdn and reset may be used interchangeably. the wdi (watchdog) and mr (manual reset) inputs also control reset output for external digital processor. figure 4 shows the general flow chart and table 7 summarizes the ad5100 functions and features. * see table 9 reset configuration register: if [0] = 0, then shdn =0 and reset = 0 if [0] = 1, then shdn =0 and reset = 1 v 1mon >uv yes no shdn=0* v 1mon on yes no shdn=0 v 2mon >off yes shdn=0 no v 3mon > threshold yes no reset=0 v 4mon > threshold yes reset=0 valid wdi yes no reset=0 mr=1 yes reset=0 no no no v 2mon level sensitive selected yes using v 4out for pwm yes no v 4mon > threshold yes v 4out =0 no v 4out =1 standard wdi selected yes no (advance wdi selected) continue monitoring valid wdi no reset=0 shdn=0 yes no (v 2mon rising edge sensitive selected) floating wdi disabled yes no floating wdi no reset=0 yes v 4mon disabled yes no default paths shdn=1 * see table 9 reset configuration register: if [0] = 0, then shdn =0 and reset = 0 if [0] = 1, then shdn =0 and reset = 1 v 1mon >uv yes no shdn=0* v 1mon on yes no shdn=0 v 2mon >off yes shdn=0 no v 3mon > threshold yes no reset=0 v 4mon > threshold yes reset=0 valid wdi yes no reset=0 mr=1 yes reset=0 no no no v 2mon level sensitive selected yes using v 4out for pwm yes no v 4mon > threshold yes v 4out =0 no v 4out =1 standard wdi selected yes no (advance wdi selected) continue monitoring valid wdi no reset=0 shdn=0 yes no (v 2mon rising edge sensitive selected) floating wdi disabled yes no floating wdi no reset=0 yes v 4mon disabled yes no default paths shdn=1 figure 4. general flow chart table 7. ad5100 functions and features input monitoring range shutdown control reset cont rol fault dete ction functions and features if not used v 1mon 6 C 30 v over/under voltage does not apply v 2mon 3 C 30 v on/off voltage tie to v 1mon , min input can bus wake up v 3mon 2.5 C 5.0 v connect to votp and threshold to minimum v 4mon 0.9 C 3.3 v additional output select disable in threshold wdi 0 C 5 v standard, advance, or leave floating watchdog selectable
preliminary technical data ad5100 rev. prj | page 11 of 32 mr 0 C 5 v highest prority on leave floating other inputs monitoring inputs v 1mon v 1mon is a high-voltage monitoring input that controls the shdn and reset functions of the external devices. in addition, it also provides a shutdown warning to the system. v 1mon monitors inputs from 6v to 30v. it has a 16-level programmable over-voltage, under-voltage (ov,uv) shutdown threshold with an 8-step 0.05ms-200ms shutdown hold time and 0.05ms-1200ms shutdown delay. the shutdown hold time means that the shutdown of the external device is held until the programmed-time is reached. on the other hand, the shutdown delay means that shuting down the external device is delayed until the programmed-time is reached. the ov threshold chosen must be greater than the uv threshold. when the shutdown is triggered either because the input has reached ov or uv threshold, such fault condition will be temporarily recorded in the fault detection register. the shdnwarn output will transition low for signaling before shutdown occurs. the occurance of shutdown is depending on how long the shutdown programmed-delay is set relative to the shdnwarn propagation delay, this feature attempts to allow the system to finish any critical house keeping tasks before shuting down the external device. the v 1mon , shutdown, and shutdown warning timing diagrams are shown in figure 5. the ranges of ov and uv thresholds are shown in table 5a and the programming codes of the selected-thresholds are found in table 5b. the defaulted ov threshold is 18.00v and uv threshold is 8.43v. simarily, the ranges of shutdown hold and delay times are shown in table 6a and the programming codes of the selected-timings are found in table 6b. the defaulted shutdown hold time is 200ms delay time is 1200ms. the voltage at v 1mon provides the power for the ad5100 but valid signal at v 2mon must be present before the internal v reg starts operation. details will be explained in the power section. * = programmable v 2mon v 2mon_on * t glitch t 2sd_delay * v 2mon_off * t 2sd_hold * t 2sd_hold * t 1sd_delay * t 1sd_hold * t 1sd_delay * v 1mon v 1mon_ov * v 1mon_uv * t glitch t 1sd_hold * shdn t 2sd_delay * shdnwarn t fd_delay t fd_delay t fd_delay t fd_delay t min # #: the duration of the t min must be shorter than t vreg_off_delay or else the ad5100 will be powered off * = programmable v 2mon v 2mon_on * t glitch t 2sd_delay * v 2mon_off * t 2sd_hold * t 2sd_hold * t 1sd_delay * t 1sd_hold * t 1sd_delay * v 1mon v 1mon_ov * v 1mon_uv * t glitch t 1sd_hold * shdn t 2sd_delay * shdnwarn t fd_delay t fd_delay t fd_delay t fd_delay t min # #: the duration of the t min must be shorter than t vreg_off_delay or else the ad5100 will be powered off figure 5. v 1mon and v 2mon shutdown timing diagrams (note reset follows shdn ). the v 1mon pin is monitored by two comparators, one for over-voltage, and one for under-voltage detection. both are designed with 1.5% hysteresis. when the v 1mon n input goes above the programmed ov threshold, the comparator will become active immediately, indicating an ov condition has occurred. due to hysteresis, the v 1mon input must be brought below the programmed ov threshold by 1.5% before the comparator will be in-active, indicating the ov condition has gone away, see figure 6.
ad5100 preliminary technical data rev. prj | page 12 of 32 when the v 1mon input drops below the programmed uv threshold, the comparator will become active immediately, indicating a uv condition has occurred. similarly due to hysteresis, the v 1mon input must be brought above the programmed uv threshold by 1.5% before the comparator will be in-active, indicating the uv condition has gone away. both v1mon comparators are used (in conjunction with hold and delay timers) to control the shdn and reset pins. v 1mon exhibits typical input resistance of 60k that users should account the loading effect. the default v 1mon ov and uv thresholds are 18.00v and 8.43v respectively. the default v 1mon shutdown hold time and shutdown delay are 200ms and 1200ms respectively. user should refer to tables 5b and 6b if they want to program different settings. v 1mon v 1mon_ov v 1mon_uv hysteresis hysteresis ov comparator active ov comparator in-active uv comparator active uv comparator in-active v 1mon v 1mon_ov v 1mon_uv hysteresis hysteresis ov comparator active ov comparator in-active uv comparator active uv comparator in-active figure 6. v 1mon hysteresis. v 2mon v 2mon is a high-voltage monitoring input that controls the shdn and reset functions of the external devices. v 2mon monitors inputs from 3v to 30v. it has a 16-level programmable turn-on, turn-off (on,off) hysteresis threshold with an 8-step 0.05ms-200ms shutdown hold time and 0.05ms-1200ms shutdown delay. by default, v 2mon is level-sensitive that the on and off thresholds are both monitored. the on threshold chosen must be greater than the off threshold. when the shutdown function is triggered by the input reaching v 2mon_off threshold, such fault condition will be temporarily recorded in the fault detection register. the shdnwarn output will transition low for signaling before shutdown occurs. the occurance of shutdown is depending on how long the shutdown programmed-delay is set relative to the shdnwarn propagation delay, this feature attempts to allow the system to finish any critical house keeping tasks before shuting down the external device. the v 2mon , shutdown, and shutdown warning pins timing diagrams are also shown in figure 5. the ranges of on and off thresholds are shown in tables 5a and the programming codes of the selected- thresholds are found in table 5b. the defaulted on threshold is 7.47v and off threshold is 6.95v. simarily, the ranges of shutdown hold and delay times are shown in table 6a and the programming codes of the selected-timings are found in table 6b. the defaulted shutdown hold time is 10ms and delay time is 100ms. v 2mon_off will be ignored if v 2mon_off > v 2mon_on but v 2mon_off cannot be = v 2mon_on. if the v 2mon is selected with rising edge triggered, only the on threshold is monitored and the off threshold is ignored. the voltage at v 1mon provides the power for the ad5100 but valid signal at v 2mon must be present before the internal v reg starts operation. details will be explained in the power section. the v 2mon pin is monitored by 2 comparators, 1 for turn-on, and 1 for turn-off detection in the level sensitive power-up mode. both are designed with 1.5% hysteresis. on the other hand, the turn-on monitoring comparator is used only if the rising edge trigger power-up mode is selected. when the v 2mon input goes above the programmed ton threshold, the comparator will become active immediately, indicating an ov condition has occurred. due to hysteresis, the v 2mon input must be brought below the programmed threshold by 1.5% before the comparator will be in-active, indicating the ov condition has gone away, see figure 7. when the v 2mon input drops below the programmed threshold, the comparator will become active immediately, indicating a uv condition has occurred. similarly due to hysteresis, the v 2mon input must be brought above the programmed threshold by 1.5% before the comparator will be in-active, indicating the uv condition has gone away. v 2mon v 2mon_on v 2mon_off hysteresis hysteresis on comparator active on comparator in-active off comparator active off comparator in-active v 2mon v 2mon_on v 2mon_off hysteresis hysteresis on comparator active on comparator in-active off comparator active off comparator in-active figure 7. v 2mon hysteresis. v 2mon exhibits typical input resistance of 60k that users should account the loading effect. the default v 2mon on and off thresholds are 7.47v and 6.95v respectively. the default v 2mon shutdown hold time and shutdown delay are 10ms and 100ms respectively. user should refer to tables 5b and 6b if they want to program different settings.
preliminary technical data ad5100 rev. prj | page 13 of 32 v 3mon v 3mon is a low-voltage monitoring input that controls the reset function of an external device. v 3mon monitors inputs from 2.5v to 5.5v. it has an 8-step programmable reset threshold with an 8-step 0.1ms-200ms reset hold time. the reset hold time means that the reset of the external device is held until the programmed-time is reached. the v 3mon and reset timing diagrams are shown in figure 8. the range of thresholds is shown in table 5a and the programming code of the selected-threshold is found in table 5b. the defaulted monitoring threshold is 4.36v. similarly, the range of reset hold time is shown in tables 6a and the programming code of the selected-timing is found in table 6b. the defaulted reset hold time is 200ms. v 3mon t glitch t rs_hold* reset v 3mon t rs_hold* t rs_delay t rs_delay * programmable v 3mon t glitch t rs_hold* reset v 3mon t rs_hold* t rs_delay t rs_delay * programmable figure 8. v 3mon reset timing diagrams the v 3mon pin is monitored by a comparator to detect an under-voltage condition. it is designed with 1.5% hysteresis. when the v 3mon input drops below the programmed uv threshold, the comparator will become active immediately, indicating a uv condition has occurred. due to hysteresis, the v 3mon input must be brought above the programmed uv threshold by 1.5% before the comparator will be in-active, indicating the uv condition has gone away, see figure 9. the v 3mon comparator is used (in conjunction with a hold timer) to control the reset pin. v 3mon exhibits typical input resistance of 50k that users should account the loading effect. the mr input has an internal resistor pull-up tov 3mon . the reset output are push-pull configured between v 3mon and gnd. v 3mon v 3mon_uv hysteresis uv comparator in-active uv comparator in-active v 3mon v 3mon_uv hysteresis uv comparator in-active uv comparator in-active figure 9. v 3mon hysteresis. the default v 3mon threshold is 4.36v. user should refer to table 5b if they want to program different setting. v 4mon v 4mon is the lowest voltage monitoring input that controls the reset function of an external device or provides a comparator output, v 4out . v 4mon monitors input from 0.9v to 3.3v. it has an 8-step programmable reset threshold with an 8-step 0.1ms to 200ms reset hold time. the v 4mon , reset, and v 4out timing diagrams are shown in figure 10. the range of thresholds is shown in table 5a and the programming code of the selected-threshold is found in tables 5b. the defaulted monitoring threshold is disabled. similarly, the range of reset hold time is shown in tables 6a and the programming code of the selected-timing is found in table 6b.
ad5100 preliminary technical data rev. prj | page 14 of 32 v 4mon t glitch t rs_hold* reset v 4mon t rs_hold* t rs_delay t rs_delay ?programmable most applications using v 4out require disabling of v 4mon triggered reset v 4out v 4mon t glitch t rs_hold* reset v 4mon t rs_hold* t rs_delay t rs_delay ?programmable most applications using v 4out require disabling of v 4mon triggered reset v 4out figure 10. v 4mon , reset , and v 4out timing diagrams the v 4mon pin is monitored by a comparator to detect an under-voltage condition. it is designed with 6% hysteresis. when the v 4mon input drops below the programmed uv threshold, the comparator will become active immediately, indicating a uv condition has occurred. due to hysteresis, the v 4mon input must be brought above the programmed uv threshold by 6% before the comparator will be in-active, indicating the uv condition has gone away, see figure 11. the v 4mon comparator is used to control the v 4out pin and also (in conjunction with a hold timer) to control the reset pin. v 4mon exhibits typical input resistance of 50k that users should account the loading effect. v 4mon v 4mon_uv hysteresis uv comparator in-active uv comparator in-active v 4mon v 4mon_uv hysteresis uv comparator in-active uv comparator in-active figure 11. v 4mon hysteresis. the default v 4mon is disabled. user should refer to table 5b if they want to program a different setting.
preliminary technical data ad5100 rev. prj | page 15 of 32 watchdog input the watch-dog input (wdi) circuit attempts to reset the system to a known good state if a software or hardware glitch renders the system processor inactive for a duration that is longer than the timeout period. there is an 8-step programmable timeout period from 100ms to 2000ms.the watchdog circuit is independent of the cpu clock that the watchdog is monitoring. watchdog is disabled during power-up. wdi starts monitoring once the reset is high. unique to ad5100, it provides a standard or advance watchdog monitoring function. in the defaulted standard watchdog mode, if wdi remains either high or low for longer than the timeout period, a reset pulse is generated in an attempt to allow the system processor to re-establish the wdi signal. the reset pulses continue indefinitely until a valid watchdog signal, a rising or falling edge signal at the wdi, is received. the internal watchdog timer clears whenever reset is asserted. the standard wdi and reset timing diagrams are shown in figure 12. reset wdi t wd t wdr t wdr t wd continuous pulses until wd awakes reset pulse t wdi reset wdi t wd t wdr t wdr t wd continuous pulses until wd awakes reset pulse t wdi figure 12. standard watchdog C pulsing reset until watchdog awakes. on the other hand, the ad5100 can be programmed to an advance watchdog mode such that when the watchdog remains inactive longer than three times the watchdog timeout period, at the forth time the shdn and reset will be asserted and released after 1 second. these actions repeat indefinitely, unless it is interferred by the user, if the processor is not responding. the advance wdi and reset timing diagrams are shown in figure 13. reset shdn wdi t wd_shdn t wd t wdr t wdr t wd 3 reset pulses 1 reset pulse shutdown at 4th reset pulse release af ter 1s t wdi reset shdn wdi t wd_shdn t wd t wdr t wdr t wd 3 reset pulses 1 reset pulse shutdown at 4th reset pulse release af ter 1s t wdi figure 13. advance watchdog C shdn asserted after three trials of reseting the watchdog. shdn released after 1 second and the cycle repeats. the range of watchdog timeout is shown in table 6a and the programming code of the selected-timeout is found in table 6b. the default timeout is 1500ms. if wdi is floating, the watchdog is disabled by default. however, floating watchdog can be enabled through i2c
ad5100 preliminary technical data rev. prj | page 16 of 32 programming such that a broken wdi connection or any unusual condition that makes wdi float will trigger the reset. enabling or disabling floating wdi can be changed dynamically provided that the otp fuse of such function is not programmed or the otp overriden function is selected. the default watchdog timeout is 1500ms. user should refer to table 6b if they want to program a different setting. manual reset manual reset mr is active low and it has an internal pull-up resistor to v 3mon . mr can be driven from a cmos logic signal. the mr and reset timing diagrams are shown in figure 14. mr has the highest priority in triggering the reset over any other monitoring inputs. mr reset < t mr_glitch t mr_delay t rs_hold* ?programmable t mr mr reset < t mr_glitch t mr_delay t rs_hold* ?programmable t mr figure 14. manual reset timing diagrams
preliminary technical data ad5100 rev. prj | page 17 of 32 outputs shutdown generator the shutdown output, shdn , is triggered by the abnormal inputs of v 1mon or v 2mon . it can also be the result of a failed watchdog input. shdn control can also be asserted low by users through i2c programming at anytime. to be explicit, the shutdown generator asserts a logic-low shdn signal based on the following conditions: 1. during power-up. 2. when v 1mon goes over or under the threshold, figure 5. 3. when v 2mon is below the turn-on threshold during the rising edge or the turn-off threshold during the falling edge in the default level sensitive mode, figure 5. 4. when the external monitoring processor cannot issue the necessary wdi signal and an advanced wdi mode is selected, figures 8 and 9. 5. i2c programmed-shutdown. the shdn signal is released after the programmable hold time. the shdn output is push-pull configured with i 2 c selectable rail voltage of either v 1mon in default or internal v reg . figure 15 shows the shdn output configurations, pull- down resistor r1 ensures shdn is pulled to ground when the ad5100 is not powered. when ad5100 is powered, m2a and m2b are both on. m2a has relatively lower impedance than m2b and r1 that the shdn remains low at shutdown. when the ad5100 settles, sw1 will be on. m1 is stronger than m2a that shdn will be pulled to the rail that makes ad5100 out of the shutdown mode. the ad5100 is likely be used to monitor and control power regulators in some applications where some regulators have the input and enable pins next to each other in fine pitch that may pose reliability concern under some abnormal conditions. to prevent this may happen, the ad5100 shutdown output features a smart-load detection that ensures the shutdown to respond for maximum protection. for example, if the car battery has not been started for an extensive period of time and a resistive dendrite may have formed across the shdn and the battery terminal (v 1mon ), the dendrite will be blown immediately as the m2a is designed with adequate current sinking capability and remains in the on position to offer such protection. in another situation where the shdn pin may be hard-shorted to any sub-30v source, the short-circuit detector will open sw2 and therefore limit the current by the high impedance m2b. figure 15. shutdown output. # = i 2 c selectable, * = default. reset generator the reset output, reset , is triggered by the abnormal input of v 3mon or v 4mon . reset activation can also be the result of the processor that is not generating the proper watchdog signal or the manual reset is triggered. to be explicit, the reset generator asserts a logic-low reset signal based on the following conditions 1. during power up 2. when v 3mon drops below the threshold, figure 8. 3. when v 4mon drops below the threshold, figure 10. 4. when shdn output is asserted, figures 5 and 13. 5. when the external monitoring processor cannot issue the necessary wdi signal, figures 12 and 13. 6. when mr is asserted, figure 14. the reset signal is asserted and maintained except when it is triggered by the wdi that will be described in the watchdog section. the reset signal is released after the programmable hold time. as shown in figure 16, the reset output is push-pull configured with the the rail voltage of v 3mon . figure 16. reset output.
ad5100 preliminary technical data rev. prj | page 18 of 32 fault detection with shutdown warning an early shutdown warning is available for the system processor to identify the source of failure and take appropriate action before shuting down the external devices. whenever the voltage at v 1mon is detected as over-voltage or under-voltage, or the voltage at v 2mon falls below the threshold, shdnwarn outputs a logic 0. if the processor sees a logic-low on this pin, the processor may issue an i2c read command to identify the cause of failure reported in the fault detect/status register. the processor may store the information in the external eeprom as a record of failure history. v 4out v 4out is an open-drain output triggered by v 4mon wth minimum propogation delay and the programmable delay does not apply. v 4out can be used as a pwm control over an external device or used as a monitoring signal. most applications using v 4out require disabling v 4mon triggered reset with an i2c command.
preliminary technical data ad5100 rev. prj | page 19 of 32 power requirements internal power the ad5100 internal power v reg is derived from v 1mon and v 2mon is used to turn ad5100 on and off with a different behavior depending on the v 2mon monitoring mode selection. by default, in the v 2mon level sensitive mode, the ad5100 turns on when the voltage at v 2mon rises above the logic threshold v 2mon_on , when v 2mon falls below the logic threshold v 2mon_off , ad5100 will trun off 2 seconds after shdn is deasserted. note that ad5100 requries 5 us to start up and that v 1mon must be applied before v 2mon . the extension of the ad5100 turn-off attempts to allow the system to complete any housekeeping tasks before the system is powered off. figure 17 shows the defaulted v 2mon and v reg waveforms. v 2mon 2.2v t glitch t vreg_on_delay 6v < v 1mon < 30v * programmable t vreg_off_delay v reg t 2sd_hold * shdn v 2mon_on * v 2mon_off * t 2sd_hold * t 2sd_delay * t vreg_off_delay v 2mon_off * v 2mon_on * t 2sd_delay * t 2sd_delay * v 2mon 2.2v t glitch t vreg_on_delay 6v < v 1mon < 30v * programmable t vreg_off_delay v reg t 2sd_hold * shdn v 2mon_on * v 2mon_off * t 2sd_hold * t 2sd_delay * t vreg_off_delay v 2mon_off * v 2mon_on * t 2sd_delay * t 2sd_delay * figure 17. internal power v reg versus v 2mon timing diagrams (default) if the pulse-sensitive v 2mon mode is selected instead, the ad5100 will not turn off when v 2mon returns to a logic low. in this mode, once the part has been powered on, it can only be power-down by an i2c power down instruction or by eliminating the supply on v 1mon pin. this feature is for the applications that use a wake up signal. v otp a 6v supply voltage is needed only during otp fuse programming. this voltage should be provided by an external source during factory programming and should have 6v/200ma driving capability. the otp programming duration depends on the numbers of programming fuses with maximum duration of 10ms. v otp is not required for normal operation. the v otp has dual functions, it is used for programming the non-volatile memory fuse arrays as well as serving as a compensation network for internal power stability. as a result, a bypass capacitor must be connected at v otp pin at all times. a low esr 10uf tantalum capacitor is recommended. figure 18. power supply requirement ad5100 achieves the otp function through blowing internal fuses. users should always apply the 6 v one-time program voltage requirement at the first fuse programming attempt. failure to comply with this requirement may lead to a change in the fuse structures, rendering programming inoperable. care should be taken when scl and sda are driven from a low voltage logic driver. ad5100 v1mon 6v - 30v 6v votp apply for otp only c2 10 f v2mon 3v - 30v
ad5100 preliminary technical data rev. prj | page 20 of 32 poor pcb layout introduces parasitic inductance that may affect the fuse programming voltage droop. therefore, it is mandatory that a 10f tantalum capacitor be placed as close as possible to the v otp pin. the value and the type of c2 chosen are important. it should provide both a fast response and larger supply current handling with minimum supply droop during programming, see figure 18. protection over-current protection if the v 1mon is shorted internally in the ad5100 to gnd, the short-circuit protection kicks in and limits subsequent current to 150ma in normal operation or 50ma when the v otp is executed. thermal shutdown when the ad5100 junction temperature is near the junction temperature limit, it will automatically shutdown and cut out the power from v 1mon . the part will resume operational when the device junction temperature returns to normal. for automotive applications, proper external protections on the ad5100 are needed in order to ensure reliable operation. the v 1mon will likely be used for battery monitoring. the v 2mon will likely be used for ignition switch or other critical inputs. as a result, these inputs may need additional protections such as emi, loaddump, and esd protections. in addition, battery input also requires reverse battery protection and short circuit fuse protection, see figure 19. esd protection it is common to require a contact rating of 8kv and a non- contact or air rating of 15kv esd protection for the automotive electronics. as a result, a esd rated protection device must be used such as mmbv27vcl, a dual 40w tvs (transient voltage suppressor) at the v 1mon and v 2mon . load dump protection a load dump is a severe overvoltage surge that occurs when the car battery is being disconnected from a spinning alternator and the resulting long-duration, high-voltage surge introduced into the supply line. as a result, external load dump protection is recommended. typically the load dump overvoltage lasts for few hundreds millisecond and peaks at around 40v to 70v while current can be as high as 1a. as a result, a load dump rated tvs d1 and d2 such as smcj17 are used to handle the surge energy. a series r is an in-line current limiting resistor, it should be adequate to limit the current without significant drop and yet small enough to not affect the input monitoring accuracy drop reverse battery protection reverse battery protection can be provided by a regular diode if the battery monitoring accuracy can be relaxed. otherwise, a 60v p-ch power mosfet, like ndt2955, can be used. because of the mosfet internal diode, the battery will first conduct through p1s body diode, as soon as the voltage reaches its source terminal, the voltage divider provides adequate gate-to- source voltage to turn on p1 and the voltage drop across the fet will be negligible. the resistor divider values are chosen such that the p1s maximum v gs is not violated and the current drawn through the battery is only a few a. emi protection for emi protection, ferrite bead or emc rated inductor such as dr331-7-103 can be used. figure 19. protection circuits
preliminary technical data ad5100 rev. prj | page 21 of 32 digital interface all programmable parameters are set through a 2-wire i 2 c protocol with read/write access to the registers. all programmable parameters can be set permanently by blowing the otp fuses at users factories. analog devices offers device programming software, which effectively replaces the need for external i 2 c controllers or host processors for otp programming in the factories. scl serial input register clock pin. shifts in one bit at a time on positive clock edges. external 1k-2.2k pull-up resistor is needed. the pull-up resistor should tie to v 3mon if it is used to monitor a sub-5v source. sda serial data input/output pin. shifts in one bit at a time on positive clock edges. msb loaded first. external 1k-2.2k pull-up resistor is needed. the pull-up resistor should tie to v 3mon if it is used to monitor a sub-5v source. ad0 i2c slave address pin. ad5100 is a slave device that will communicate with a master if the ad0 bit in the protocol matches with the logic state of the ad5100s ad0 pin. table 8 and figure 20 show the example with two ad5100 devices operate on the same serial bus independently. table 8. slave address decoding scheme ad0 program ming bit ad0 device pin device address ed 0 0v 0x2e (u1) 1 5v 0x2f (u2) figure 20. two ad5100 devices on one bus the master-device output bus-line drivers are open-drain pull- downs in a fully i 2 c compatible interface. ad5100 register map table 9 outlines the address pointer registers used to configure and control all parameters and functions in the ad5100. table 10 shows the address pointer register structure. table 9 also outlines if registers are writable, readable, or permanently settable. all registers are single-port, meaning they have the same address for read and write operations. the ad5100 ships from its manufacturing factory with default power-up values as listed in the last column. the user can experiment with different settings in the various threshold, delay and configuration registers. once enough evaluation is done, the user can program their own power-up default values via a one time program (otp) feature. when all desired settings have been programmed (or the user is satisfied with the manufacturers defaults), a lock-out bit can be set to prevent further/erroneous settings from being programmed. some users will use the ad5100 as a set and forget device, i.e. program some default values and never need to change these over the life of the application. however some users will require on the fly flexibility, i.e. the ability to change settings to values other than those they choose as their defaults. an additional feature of the ad5100 is the ability to temporarily over-ride the otp executed settings and still allows users to program the parts dynamically in the field. all over-ride values will revert back to otp executed settings once the ad5100 is power cycled. register writing, reading, otp & over-ride are explained later in the i2c section. master sda scl ad0 sda scl ad0 sda scl 5v rp rp 5v a d5100 a d5100 u2 u1
ad5100 preliminary technical data rev. prj | page 22 of 32 table 9. ad5100 register map regi ster add ress re ad / w rit e permane ntly settable register name & bit description pre-otp power on default (1) 0x01 r/ w y v 1mon over-voltage threshold [3:0] C 4 bits used to program v 1mon ov threshold [7:4] C reserved 0x00 (18.00 v) 0x02 r/ w y v 1mon under-voltage threshold [3:0] C 4 bits used to program v 1mon uv threshold [7:4] C reserved 0x00 (8.43 v) 0x03 r/ w y v 2mon turn-on threshold [3:0] C 4 bits used to program v 2mon ton threshold [7:4] C reserved 0x00 (7.47 v) 0x04 r/ w y v 2mon turn-off threshold [3:0] C 4 bits used to program v 2mon toff threshold [7:4] C reserved 0x00 (6.95 v) 0x05 r/ w y v 3mon reset threshold [2:0] C 3 bits used to program v 3mon reset threshold [7:3] C reserved 0x00 (4.36 v) 0x06 r/ w y v 4mon reset threshold [2:0] C 3 bits used to program v 4mon reset threshold [7:3] C reserved 0x00 (disabled) 0x07 r/ w y v 1mon ov/uv triggered shdn hold [2:0] C 3 bits used to program v 1mon ov/uv triggered shdn hold time [7:3] C reserved 0x00 (200 ms) 0x08 r/ w y v 1mon ov/uv triggered shdn delay [2:0] C 3 bits used to program v 1mon ov/uv triggered shdn delay time [7:3] C reserved 0x00 (1200 ms) 0x09 r/ w y v 2mon turn-on triggered shdn hold [2:0] C 3 bits used to program v 2mon ton triggered shdn hold time [7:3] C reserved 0x00 (10 ms) 0x0 a r/ w y v 2mon turn-off triggered shdn delay [2:0] C 3 bits used to program v 2mon toff triggered shdn delay time [7:3] C reserved 0x00 (100 ms) 0x0 r/ y reset hold 0x00
preliminary technical data ad5100 rev. prj | page 23 of 32 b w [2:0] C 3 bits used to program reset hold time [7:3] C reserved (200 ms) 0x0 c r/w y watchdog timeout [2:0] C 3 bits used to program watchdog timeout time [7:3] C reserved 0x00 (1500 ms) 0x0 d r/ w y reset configuration [0] C 0 - reset is active when shdn is active 1 - reset is not active when shdn is active [1] C reserved [2] C 0 - enable v 4mon over threshold to cause reset 1 - prevent v 4mon over threshold to cause reset (for v 4out application) [3] C 0 - prevent floating wdi to cause reset 1 - enable floating wdi to cause reset [7:4] C reserved 0x00 0x0e r/ w y shdn rail voltage configuration [2:0] C reserved [3] C 0 - shdn rail = v 1mon 1 - shdn rail = vreg [7:4] C reserved 0x00 0x0f r/ w y watchdog mode [2:0] C reserved [3] C 0 C standard mode 1 C advanced mode [7:4] C reserved 0x00 0x15 r/ w y program lock fuse (inhibit further programming) [2:0] C reserved [3] C 0 C fuse programming allowed 1 C fuse programming disabled [7:4] C reserved 0x00 0x16 r/ w n special functions 1 [0] C 0 C otp enable a inactive 1 C otp enable a active [1] C 0 - otp enable b inactive 1 - otp enable b active [2] C 0 C software assertion of shdn inactive 0x00
ad5100 preliminary technical data rev. prj | page 24 of 32 1 C software assertion of shdn active [3] C 0 - over-ride of permanent settings inactive 1 - over-ride of permanent settings active [7:4] C reserved 0x17 r/ w n special functions 2 [0] C 0 C software power-down of ad5100 inactive 1 C software power-down of ad5100 active (2) [7:1] C reserved 0x00 0x18 r/ w n disable special functions (3) [0] C 0 C allow over-ride function 1 C disable further over-ride function [1] C 0 C allow otp function 1 C disable otp function [2] C 0 C allow manufacturer test-modes 1 C disable manufacturer test-modes [3] C 0 C allow software power-down function 1 - disable software power-down function [4] C 0 C allow software assertion of shdn function 1 C disable software assertion of shdn function [7:5] C reserved 0x00 0x19 r- on ly n fault detect & status register [3:0] C these 4 level triggered bits indicate the current state of the comparators monitoring the v 1mon and v 2mon input pins. [0] C a 1 indicates v 2mon input < v 2mon off threshold [1] C a 1 indicates v 2mon input > v 2mon on threshold [2] C a 1 indicates v 1mon input < v 1mon uv threshold [3] C a 1 indicates v 1mon input > v 1mon ov threshold [6:4] C these are fault detection bits can be decoded to indicate one or more conditions were present when a shdn event occurred. these bits are edge triggered. 000 C none 001 C v 1mon uv only 010 C v 1mon ov only 011 C never occur 100 C v 2mon below off only 101 C v 1mon uv and v 2mon below off both occur 110 C v 1mon ov and v 2mon below off both occur 0x00
preliminary technical data ad5100 rev. prj | page 25 of 32 111 C never occur [7] C reserved notes 1. values ad5100 has when shipped from manufacturers factory. 2. v 2mon must be 0v for software power down. 3. these register bits are set only. to clear them the ad5100 must be power cycled. in some cases the ad5100 may be connected to a n i 2 c bus with lots of activity. setting these bits is an added means of ensu ring any erroneous activity on the bus does not cause ad5100 spec ial functions to become active. i2c serial interface control of the ad5100 is accomplished via an i 2 c compatible serial bus. the ad5100 is connected to this bus as a slave device (the ad5100 has no master capabilities). the ad5100 has a 7-bit slave address. the six msbs are 010111 and the lsb is determined by the state of the a0 pin. therefore when a0 is low, the ad5100 slave address is 01011110 and 0101111 otherwise. therefore the a0 pin allows the user to connect two ad5100s to the same i 2 c bus provided the two devices comply with the configurations shown in figure 20. the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when sda goes from high-to-low while scl is high. the following byte is the slave address byte, which consists of the 7-bit slave address followed by an r/ w bit which determines whether data is read from or written to the slave device 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low-to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition. in the read mode, the master issues a no acknowledge for the 9 th clock pulse, (i.e., the sda line remains high). the master then brings the sda line low before the 10 th clock pulse and then high during the 10 th clock pulse to establish a stop condition. for the ad5100, write operations contain either one or two bytes, while read operations contain one byte. the ad5100 makes use of an address pointer register . the address pointer register does not have and does not require an address, because it is the register to which the first data byte of every write operation is written automatically. this data byte is an address pointer that sets up one of the other registers for the second byte of the write operation or for a subsequent read operation. table 10 shows the structure of the address pointer register. bits [6:0] signify the address of the register that is to be written to or read from. bit [7] is used when otp mode is invoked (use of this bit is explained later in the otp section), and should be 0 for normal write/read operations. table 10 C address pointer register structure bit # [7] [6] [5] [4] [3] [2] [1] [0] function otp en ap6 ap5 ap4 ap3 ap2 ap1 ap0 writing data to ad5100 when writing data to the ad5100, the user begins by writing an address byte followed by the r/ w bit set to 0. the ad5100 will acknowledge (if the correct address byte is used) by pulling the sda line low during the 9 th clock pulse. the user then follows with two data bytes. the first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. the second byte is the data to be written to the internal data register. after each byte the ad5100 acknowledges by pulling the sda line low during the 9 th clock pulse. figure 21 illustrated this operation. sda frame 1 slave address byte frame 2 address pointer byte frame 3 data byte scl ack. by ad5100 ack. by ad5100 ack. by ad5100 stop by master start by master 0 1 0 1 1 ad0 r/w otp ap6 ap5 ap4 ap3 ap2 ap1 ap0 d7 d4 d3 d2 d1 d0 03437-0-035 1 d6 d5
ad5100 preliminary technical data rev. prj | page 26 of 32 figure 21 C writing a register address to the address pointer register, then writing data to the selected register reading data from ad5100 when reading data from an ad5100 register there are two possibilities: 1. if the ad5100s address pointer register value is unknown or not at the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. this is done by performing a write to the ad5100 as before, but only a value containing the register address is sent, because data is not to be written to the register. this is shown in figure 22. a read operation is then performed consisting of the serial bus address, r/ w bit set to 1, followed by the data byte from the data register. this is shown in figure 23. 2. if the address pointer is known to be already at the desire address, data can be read from the corresponding data register without first writing to the address pointer register. figure 22. dummy write to set proper address pointer. figure 23. read data from the address pointer register. table 11 shows the read-back data byte structure. bits [6:0] contain the data from the register just read. bit [7] only has significance when otp mode is being used, and should be ignored for normal read operations. the majority of ad5100s registers are 4-bits wide, with only the status/fdr register and disable special function register by 7 bit and 5 bits wide respectively. table 11 C read-back data byte structure bit # [7] [6] [5] [4] [3] [2] [1] [0] function otp okay d6 d5 d4 d3 d2 d1 d0 permanent setting of ad5100 registers (otp function) when the user wants to permanently program settings to the ad5100, the one time program (otp) function is invoked. to complete a permanent program cycle for a particular register, the following sequence should be used: 1. set bit [0] in register 0x16 using a normal write operation 2. set bit [1] in register 0x16 using a normal write operation 3. apply a 6v (200ma) voltage source to the otp pin. this provides the current for the programming cycle. 4. write the desired permanent data to the register of choice, using a write operation with the otp bit set to 1 in the address pointer byte. when the write cycle has been completed, the user should allow minimum of 30ms for the ad5100 to perform the permanent setting of the internal register. the user has the opportunity to check whether the ad5100 programmed correctly by performing a read cycle, and monitoring the state of bit [7] ( otp okay ). otp okay = 1 indicates the ad5100 programmed correctly otp okay = 0 indicates the ad5100 programmed incorrectly note: read-back of the otp okay bit is only available for the read cycle following immediately after the program cycle. if a write or read of a different register is done immediately after the program cycle, then the opportunity for verifying if the programming was successful will have been missed. figure 24 shows the recommended way of performing a program then read-back and verify of the v 1mon over-voltage register, (assuming steps 1-3 above have already been done). sda frame 1 slave address byte frame 2 read data byte scl ack. by ad5100 no ack. by master stop by master start by master 0 1 0 1 1 ad0 otp ok d6 d5 d4 d3 d2 d1 d0 r/w 03437-0-037 1 sda frame 1 slave address byte frame 2 address pointer byte scl ack. by ad5100 ack. by ad5100 stop by master start by master 0 1 0 1 1 ad0 r/w otp ap6 ap5 ap4 ap3 ap2 ap1 ap0 03437-0-035 1
preliminary technical data ad5100 rev. prj | page 27 of 32 programming sequence s 0x5c a 0x01 a 0x8f a p delay s 0x5d comment start slave addr ess + write ack set v 1mon ov thres hold ack otp at setti ng 15 ack stop wait for 30ms start slave addr ess + read figure 24. example of executing otp and a successful validation when all default registers have been programmed, the lock bit should be set. user programmed defaults wont become active until the first power cycle after the lock bit is set. programming the lock bit is done in exactly the same manner as all other registers. temporary over-ride of default settings (over-ride function) as stated previously in the register map section, even with the lock bit set, it is possible to temporarily over-ride the default values of any of the permanently programmable registers. to over-ride a permanent setting in a particular register, the following sequence should be used: 1. set bit [3] in register 0x16 (special functions 1) 2. write the desired temporary data to the register of choice while the over-ride bit is set in register 0x18, the user may over- ride any registers they wish by simply writing to them with new data. to revert an over-ridden register back to its default setting, the following sequence should be used: 1. clear bit [3] in register 0x16 2. write a dummy byte to the register of choice clearing the over-ride bit in register 0x18 does not cause all over- ridden registers to revert back to their defaults at the same time. for example, imagine the user had over-ridden registers 0x01, 0x02 & 0x03. if the user now cleared the over-ride bit in register 0x16 and wrote a dummy byte to register 0x01, it would revert back to its default value. however registers 0x02 & 0x03 would still contain their over-ride data. to revert both registers back to their defaults, the user must write dummy data to each register individually. power cycling the ad5100 will also revert all registers back to their programmed defaults. controlling the ad5100 there are two ways to control the ad5100. users can apply the ad5100 evaluation software for one time programming the devices in the factory without ever reprogramming the parts in the fields. they can also design or make use of the on-board i 2 c controllers for programming the ad5100. the later is necessary for any dynamic or field programming applications.
ad5100 preliminary technical data rev. prj | page 28 of 32 applications car battery and infotainment system supply monitoring the ad5100 has two high-voltage monitoring inputs with shutdown and reset controls over external devices. for example, the v 1mon and v 2mon can be used to monitor the signals from a car battery and an ignition key in an automobile, respectively. such application is shown in figure 25. the shutdown output can be connected to the shutdown pin of an external regulator to prevent false conditions such as a weak battery or overcharging battery by an alternator. the reset output can be used to reset the processor in the event of a hardware or software malfunction. an example of the input and output responses of this circuit is shown in figure 26. figure 25. typical dsp in car infotainment application.
preliminary technical data ad5100 rev. prj | page 29 of 32 battery ignition vreg shdn +5v +3.3v reset wdi mr ov uv uv shutdown +5v brownout reset shutdown enable reset < t glitch t vreg_off_delay wdi reset mr reset t vreg_on_delay up failed reset wdi reset up failed shutdown hi-z hi-z v2mon off shutdown shutdown enable reset battery ignition vreg shdn +5v +3.3v reset wdi mr ov uv uv shutdown +5v brownout reset shutdown enable reset < t glitch t vreg_off_delay wdi reset mr reset t vreg_on_delay up failed reset wdi reset up failed shutdown hi-z hi-z v2mon off shutdown shutdown enable reset figure 26. examples of shdn and reset responses of circuit shown in figure 25.
ad5100 preliminary technical data rev. prj | page 30 of 32 battery monitoring with fan control v 4mon can be used with v 4out intandem to form a simple pwm control circuit. for example as shown in figure 27, when a temperature sensor output connects to the v 4mon input, with the proper threshold level set, v 4out outputs high whenever the temperature goes above the threshold. this turns on the fet switch which activates the fan. when vtemp drops below the threshold, v 4out decreases which turns off the fan. ad5100 v 1mon v 2mon v 3mon v 4mon battery ignition vreg vtemp p shdn reset v 4out sd_wrn scl sda clk sd vreg clk miso/mosi tmp35 vtemp battery pa vreg /mr /mr wdi wdi /mr wdi ad5100 v 1mon v 2mon v 3mon v 4mon battery ignition vreg vtemp p shdn reset v 4out sd_wrn scl sda clk sd vreg clk miso/mosi tmp35 vtemp battery pa vreg /mr /mr wdi wdi /mr wdi figure 27. power amp monitoring and fan control v temp v 4out note: v 4mon reset disabled v 4mon threshold v temp v 4out note: v 4mon reset disabled v 4mon threshold figure 28. v 4out with respect to vtemp withv 4mon reset disabled in circuit shown in figure 27. battery state of charge indicator and shutdown early warning monitoring in the automotive application, the system designer may set the battery threshold to the lowest level in order to allow an automobile to start at the worst case condition. if the battery remains at the low voltage level, it is indeed a poor battery. however, there is no way to warn the driver. as a result, the system designer may use v 4out as the battery warning indicator. by stepping down the battery voltage monitored at v 4mon , the led is lit which gives a battery replacement warning. the circuit is shown in figure 29. ad5100 v 2mon v 1mon v 4mon ignition battery p v 4out scl sda clk clk miso/mosi sd_wrn shdn ad5100 v 2mon v 1mon v 4mon ignition battery p v 4out scl sda clk clk miso/mosi sd_wrn shdn figure 29. battery state of charge indication
preliminary technical data ad5100 rev. prj | page 31 of 32 psuedo can bus wake up mode using the ad5100 as indicated in figure 30, the microprocessor can control its own power down sequence using the can bus wake up signal. the operator must select the last setting rising edge trigger/can wake up mode in the v 2mon tur n of f threshold parameter (the i2c write command is s 01011100 a 00000100 a 00001001 a p). now when the rising edge of the can bus wake up signal is detected by v 2mon , the ad5100 is powered up with shutdown pulls high. the external regulator is turned on to supply power to the microprocessor. a reset pulse train will be generated at the reset output if there is no watchdog activity. the pulse continues until the correct watchdog signal appears at the ad5100 wdi pin. the shutdown pin remains high as long as the ad5100 continues to receive the correct watchdog signal. when the microprocessor finishes its housekeeping tasks or powers down the software rountine, it stops sending a watchdog signal. in response, the ad5100 generates a reset. the shutdown pin will be pulled low 2 seconds after and the regulator output drops to 0v, which shuts down the microprocessor. at that point, the ad5100 goes into sleep mode. can wake up pulse(s) ad5100 v 1mon v 2mon battery shdn reset sd vreg wdi v i v o p i/o rs v dd i/o i/o scl sda can wake up pulse(s) ad5100 v 1mon v 2mon battery shdn reset sd vreg wdi v i v o p i/o rs v dd i/o i/o scl sda figure 30. can wake up mode reset wdi shdn v 2mon notes ?6v < v 1mon < 30v ?select v 2mon_off = rising edge trigger/can wake up mode scl sda sda write scl reset wdi shdn v 2mon notes ?6v < v 1mon < 30v ?select v 2mon_off = rising edge trigger/can wake up mode scl sda sda write scl figure 31. can bus operation of circuit shown in figure 30.
ad5100 preliminary technical data rev. prj | page 32 of 32 figure 32. qsop-16 mechanical dimension ordering guide model temperature range package code package description full container quantity branding ad5100yrqz- rl7 1 ?40c to +125c rq-16 qsop-16 1,000 tbd a ad5100yrqz 1 ?40c to +125c rq-16 qsop-16 98 tbd AD5100EVAL evaluation board 1 1 z = pb-free part. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr05692-0-2/06(prj)

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